BIST: required for embedded DRAM

Introduction In the virtual component (VC) integration business, the embedded DRAM is a key VC to realize high bit density and high bandwidth performance, thus the low-cost testing of DRAM-integrated LSI is an emerged problem. The DRAM test usually includes a fail-bit (address) search to repair the memory cell defects with redundancy, requiring long time for wafer probing. A DRAM BIST drastically reduces time of both wafer probing and final test, compared with test by only ATE. In the VC-LSI testing, BIST for embedded DRAM is also required to reduce the test time and to realize VC test isolation.